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Kompilacja Visual DSP++

romanmarek 02 Cze 2012 11:56 1585 0
  • #1 02 Cze 2012 11:56
    romanmarek
    Poziom 2  

    Mam taką prośbę panowie nie praacowałem nigdy na tym środowisku, ale na zajęciach udało mi się skompilować pewien program i teraz rozię z tego sprawozdanie i nie mogę uruchonmić go ponownie w domu z czym może być problem?

    oto kod źródłowy :

    /*
    skeleton_main.c Rev. 1.10

    Evaluation board: ALS-G3-1369
    Environment: VisualDSP++ Rev. 4.5 + July 2006 Upgrade

    The SKELETON PROJECT is intended to use as base
    for LABINVERTER control application

    First release in 03.2008

    ALFINE P.E.P., 12.2008
    */


    #include <filter.h>
    #include <21369.h>
    #include <def21369.h>
    #include <Cdef21369.h>
    #include <signal.h>
    #include <math.h>
    #include <sru21369.h>
    #include "..\Common_files\sys_def.h"
    #include "..\Common_files\sys_serv.h"
    #include "..\Common_files\1369_cons.h"


    //void PWM_isr(int signal); //PWM interrupt service routine

    //void INVERR_isr(int signal); //DAI interrupt (Inverter ERROR service)

    void ADC_isr(int signal); //ADC interrupt service routine


    //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    void SYS_Init(void); //System Setup - OBLIGATORY for Eval Board
    //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

    //System CLOCKS
    //#define CLK_IN_FREQ 24e6 //Processor Input Clock freq. [Hz] - for Board Rev. 0.10
    #define CLK_IN_FREQ 20e6 //Processor Input Clock freq. [Hz] - for Board Rev. 0.11

    #define CLOCK_MULT PLLM18 //Effective ext. Clock multiplikator (DSP PLL Feature)
    //check "def21369.h" for available PLLMx factors
    #define CORE_FREQ CLOCK_MULT*CLK_IN_FREQ //Core Clock freq. [Hz]


    //PWM Generator definitions
    #define PWM_MODE 0x23 //Center-Aligned, Paired Mode, Single Update Mode,
    //PWM IRQ Enabled, PWM signals active LOW
    #define PWM_FREQ 10e3 //PWM Carrier freq. [Hz]
    #define PWM_DIV (int)(CORE_FREQ/(4*PWM_FREQ)) //Divisor for PWM in SINGLE_UPDATE Mode
    #define PWM_DT 3.5 //Dead time value [us]
    #define DT_DIV (int)(1e-6*PWM_DT*CORE_FREQ/4) //Dead time divider

    //Sampling/system parameters
    #define ADC_CONV_FREQ 1e5 //ADCs sample rate [Hz]
    #define FRS_DIV CLK_IN_FREQ/ADC_CONV_FREQ //divider for PCG

    #define ADC_CONFIG 0x0000fc00 //ADC cofiguration word
    //All channels active, +/-2xVREF input voltage range
    //external VREF, on-chip VREF buffers enabled

    ADC_Util data_in_1, data_in_2; //data from ADCs
    DAC_Util data_out; //data for DAC


    //User/application definitions and variables
    #define PI 3.1415927
    #define PERIOD 100
    #define N 100
    #define dlt_A_ref 0.1

    float sgn(float sgn_we);

    int status, duty=0, t=0;
    int i;





    unsigned int kbd_state;

    float A_ref=0, s_ref=0;
    float we1[N],wy[N];
    float a0,a1,a2,a3,a4,a5,a6,a7,a8,a9;
    float x_1, x_2, x_3, x_4, x_5, x_6, x_7, x_8, x_9, x_10;
    float we;

    main()
    {

    //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    SYS_Init(); //System initilization - OBLIGATORY program line !!!
    //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!


    //INV_ENA(); //enable inverter interface

    clr_LCD(); //clear LCD memory

    //lprintf_LCD(0,"%s","ALS-G3-1369 Rev.1.10"); //system message

    //lprintf_LCD(64,"%s","Project: skelton.dpj"); //system message

    //lprintf_LCD(84,"%s","A_ref="); //system message

    lprintf_LCD(0,"%s","DZIALA!!!");
    lprintf_LCD(64,"%s","prosimy >= 4");


    //interrupt(SIG_SPIL, PWM_isr); //Enable low priority PWM interrupt (SPI IVT)

    //interrupt(SIG_DAIH, INVERR_isr); //enable DAI/HIGH priority interrupt

    interruptf(SIG_IRQ0, ADC_isr); //enable external No 0 interrupt

    INV_START(); //activation own inverter control block




    //wpisywanie danych wejsciowych do tablicy
    for (i=0;i<N; i++)
    we1[i]=sgn(sinf(10*2*PI*i/N));

    //wait_ms(1000);

    //----------------------------------------

    //wspolczynniki filtru

    a0=0.2;
    a1=0.1;
    a2=0.2;
    a3=0.1;
    a4=0.1;
    a5=0.1;
    a6=0.1;
    a7=0.1;
    a8=0.4;
    a9=0.1;

    //-------------------------

    // wpisywanie danych wyjsciowych


    for (i=0;i<N;i++)
    {
    wy[i]=a0*we1[i]+a1*x_1+a2*x_2+a3*x_3+a4*x_4+a5*x_5+a6*x_6+a7*x_7+a8*x_8+a9*x_9;
    x_9=x_8;
    x_8=x_7;
    x_7=x_6;
    x_6=x_5;
    x_5=x_4;
    x_4=x_3;
    x_3=x_2;
    x_2=x_1;
    x_1=we1[i];
    }
    //----------------------


    while(1)
    {
    //lprintf_LCD(90,"%f4.1",A_ref); //print current A_ref value

    /*kbd_state = read_kbd();

    switch(kbd_state)
    {
    case K1: if((A_ref+dlt_A_ref)<1.0) //A_ref UP
    A_ref=A_ref+dlt_A_ref;
    break;
    case K2: if((A_ref-dlt_A_ref)>0) //A_ref DOWN
    A_ref=A_ref-dlt_A_ref;
    break;

    default: break;
    }
    */
    lprintf_LCD(84,"%.2f",we);
    //wait_ms(200); //delay

    //idle(); //put DSP core in idle state for energy conservation
    }


    asm("nop;");

    }



    void ADC_isr(int signal)
    {

    //set_flag(SET_FLAG1, CLR_FLAG); //for debuging purposes only

    //Place USER code here
    //...
    #define DAC_SCALE 32767 //for scaling data for DAC


    ADC1_Data_In(ADC_CONFIG, &data_in_1); //read data from ADC No 1
    //ADC2_Data_In(ADC_CONFIG, &data_in_2); //and ADC No 2

    data_in_1.Ch_1>>16;
    we = data_in_1.Ch_1*0.000152;



    ////data_out.Ch_A = DAC_SCALE*s_ref; //put data into 'DAC_Util' structure
    //data_out.Ch_B = data_in_1.Ch_1; //put data from ADC No 1/channel 1 directly to DAC channel B
    //data_out.Ch_C = data_in_1.Ch_2; //put data from ADC No 1/channel 2 directly to DAC channel C
    //data_out.Ch_D = data_in_2.Ch_1; //put data from ADC No 2/channel 1 directly to DAC channel D


    ////DAC_Data_Out(&data_out); //put data into DAC

    //set_flag(SET_FLAG1, SET_FLAG); //for debuging purposes only

    }


    /*
    void PWM_isr(int signal)
    {
    set_flag(SET_FLAG1, CLR_FLAG); //for debuging purposes only

    *pPWMGSTAT = PWM_STAT0 | PWM_STAT1; //Write into PWMGSTAT to reset PWM_INT bits !


    //Place USER code here
    //...
    s_ref=A_ref*sinf(2*PI*t++/PERIOD); //software generated a SIN function
    if(t==PERIOD)
    t=0;

    PWM_Duty(PWM_DIV/4*s_ref,-PWM_DIV/4,PWM_DIV/4); //change PWM duty cycle
    //PWM carrier waveform in channel PWM0/1
    //is modulated sinusoidally

    WDG_RFSH(); //inverter interface WATCHDOG refreshing
    //- neccessary for enabling inverter interface

    set_flag(SET_FLAG1, SET_FLAG);
    }



    void INVERR_isr(int signal)
    {
    //set_flag(SET_FLAG1, TGL_FLAG); //for debuging purposes only

    status = *pDAI_IRPTL_H; //clear DAI_H interrupt latch bit

    //Place User code here
    //...

    }
    */


    void SYS_Init(void)
    {


    //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    PLL_SDCLK_Init(CLOCK_MULT); //OBLIGATORY program line
    //due to system configuration needs
    //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!


    //Configure SRU
    //Generating Code for connecting:DAI_PIN19 to MISCA0
    //- INVERR signal service
    SRU (LOW, PBEN19_I);
    SRU (DAI_PB19_O, MISCA0_I);

    //Interrupt system configuration
    //- DAI
    *pDAI_IRPTL_FE = SRU_EXTMISCA0_INT; //FALLING EDGE sensitivity
    *pDAI_IRPTL_PRI = SRU_EXTMISCA0_INT; //PRIORITY REG must be SET UP to take effect !


    *pSYSCTL = *pSYSCTL | IRQ0EN; //configure FLAG0 as ext. interrupt source
    asm volatile ("bit set MODE2 1;"); //IRQ0 - edge activated

    ADC1_Data_In(ADC_CONFIG, &data_in_1); //first configure ADC No 1
    ADC2_Data_In(ADC_CONFIG, &data_in_2); //and ADC No 2

    Set_PCG(FRS_DIV); //activate ADCONV_START signal (PCG_A of P2)

    PWM10_Init(PWM_MODE,PWM_DIV,DT_DIV); //PWM unit initializaion

    wait_ms(200); //wait for VCC stabilization due to LCD controller demanding

    init_LCD(); //LCD module initialization
    }

    float sgn(float sgn_we)
    {
    if (sgn_we<0) return -1;
    else if (sgn_we>0) return 1 ;
    else return 0;
    }

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