Włączenie przerwania polega na ustawieniu bitu w rejestrze maskującym czy flagowym ?
Czy wolisz polską wersję strony elektroda?
Nie, dziękuję Przekieruj mnie tamCytat:EIMSK – External interrupt mask register
• Bit 0 – INT0: External interrupt request 0 enable
When the INT0 bit is set (one) and the I-bit in the status register (SREG) is set (one), the external
pin interrupt is enabled. The interrupt sense Control0 bits 1/0 (ISC01 and ISC00) in the
external interrupt control register A (EICRA) define whether the external interrupt is activated on
rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of external
interrupt request 0 is executed from the INT0 interrupt vector.
Cytat:General Interrupt Control Register – GICR
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external
pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
general Control Register (MCUCR) define whether the external interrupt is activated on rising
and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from the INT0 Interrupt Vector.