The correct disable procedure is (except when receive-only mode is used):
2. Wait until TXE=1 and then wait until BSY=0 before disabling the SPI.
Note: During discontinuous communications, there is a 2 APB clock period delay between the
write operation to the SPI_DR register and BSY bit setting. As a consequence it is mandatory to wait first until TXE is set and then until BSY is cleared after writing the last