witam
czy moze mi to ktos przetlumaczyc fragment o dzialaniu ukaldu ktore to dzialanie staram sie zrozumiec? PROSZE.
probuje sam ze slownikiem ale wychodzi jakis bezsens za duzo fachowych slowek niestety..
bede bardzo wdzieczny.
The decoded digital data is transformed into analog format by an 18-bit oversampling multi-bit sigmadelta
DA-converter. The oversampled output is low-pass filtered by an on-chip analog filter. The output
rate of the DA-converter is always 1/4 of the clock rate, or 128 times the highest usable sample rate. For
instance for a 24.576 MHz clock, the DA-converter operates at 128x48 kHz, which is 6.144 MHz. If the
input sample rate is other than 48 kHz, it is internally converted to 48 kHz by the DAC. This removes the
need for complex PLL-based clocking schemes and still allows the use of several sample rates with one
fixed master clock frequency.
czy moze mi to ktos przetlumaczyc fragment o dzialaniu ukaldu ktore to dzialanie staram sie zrozumiec? PROSZE.
probuje sam ze slownikiem ale wychodzi jakis bezsens za duzo fachowych slowek niestety..
bede bardzo wdzieczny.
The decoded digital data is transformed into analog format by an 18-bit oversampling multi-bit sigmadelta
DA-converter. The oversampled output is low-pass filtered by an on-chip analog filter. The output
rate of the DA-converter is always 1/4 of the clock rate, or 128 times the highest usable sample rate. For
instance for a 24.576 MHz clock, the DA-converter operates at 128x48 kHz, which is 6.144 MHz. If the
input sample rate is other than 48 kHz, it is internally converted to 48 kHz by the DAC. This removes the
need for complex PLL-based clocking schemes and still allows the use of several sample rates with one
fixed master clock frequency.