PWM na AT91SAM7S64 z FreeRTOS - konfiguracja kanału 0 nie działa

void
audio_hw_conf(void)
{
  // Confiugre PIO (Parallel Input/Output Controller).
  AT91C_BASE_PIOA->PIO_PDR = AT91C_PWMC_CHID0;                                           // Enable peripheral function.
  AT91C_BASE_PIOA->PIO_ASR = AT91C_PWMC_CHID0;                                           // Peripheral function A.


  // Configure PMC (Power Management Controller).
  AT91C_BASE_PMC->PMC_PCER = AT91C_ID_PWMC;                                              // Power up PWM Controller.


  // Configure AIC (Advanced Interrupt Controller).
  AT91F_AIC_ConfigureIt(7, AT91C_AIC_PRIOR_1, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
                    &audio_pwm0_isr_wrapper);
  AT91C_BASE_AIC->AIC_IECR = 0x1 << 7;


  // Configure PWMC (Pulse Width Modulation Controller).
  AT91C_BASE_PWMC->PWMC_MR = 0;                                                          // Clear mode register.
  AT91C_BASE_PWMC->PWMC_CH[AT91C_PWMC_CHID0].PWMC_CMR =
  AT91C_PWMC_CPRE_MCK_1024 | AT91C_PWMC_CPOL;                                            // MCK/1024 and polarity 1.
  AT91C_BASE_PWMC->PWMC_CH[AT91C_PWMC_CHID0].PWMC_CPRDR = 0x00004650;                    // Period set to 1sec.
  AT91C_BASE_PWMC->PWMC_CH[AT91C_PWMC_CHID0].PWMC_CDTYR = 0x00002328;                    // 50% duty cycle.
  AT91C_BASE_PWMC->PWMC_IER = AT91C_PWMC_CHID0;                                          // Enable interrupt from chn0.
  AT91C_BASE_PWMC->PWMC_ENA = AT91C_PWMC_CHID0;                                          // Enable channel 0.
}


// Audio PWM channel 0 interrupt handler.

void
audio_pwm0_isr_handler (void)
{
  //AT91C_BASE_PWMC->PWMC_CH[AT91C_PWMC_CHID0].CUPDR = newvalue
  AT91C_BASE_AIC->AIC_EOICR = 0;
}


// Audio PWM channel 0 wrapper.

void
audio_pwm0_isr_wrapper (void)
{
  portSAVE_CONTEXT();
  audio_pwm0_isr_handler();
  portRESTORE_CONTEXT();
}

// Configure PMC (Power Management Controller).
  AT91C_BASE_PMC->PMC_PCER = AT91C_ID_PWMC;                                              // Power up PWM Controller.

// Configure PMC (Power Management Controller).
  AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PWMC;                                              // Power up PWM Controller.

 AT91PS_PMC     pPMC = AT91C_BASE_PMC;

    //* Set Flash Waite sate
	//  Single Cycle Access at Up to 30 MHz, or 40
	//  if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
	    AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;

    //* Watchdog Disable
        AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;

	//* Set MCK at 47 923 200
    // 1 Enabling the Main Oscillator:
        // SCK = 1/32768 = 30.51 uSeconde
    	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
       pPMC->PMC_MOR = ((( AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN ));
        // Wait the startup time
        while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
	// 2 Checking the Main Oscillator Frequency (Optional)
	// 3 Setting PLL and divider:
		// - div by 5 Fin = 3,6864 =(18,432 / 5)
		// - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
		// for 96 MHz the erroe is 0.16%
		//eld out NOT USED = 0 Fi
       pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |
                         (AT91C_CKGR_PLLCOUNT & (28<<8)) |
                         (AT91C_CKGR_MUL & (25<<16)));

        // Wait the startup time
        while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
	// 4. Selection of Master Clock and Processor Clock
        // select the PLL clock divided by 2
       pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));

        pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
}

AT91C_BASE_PWMC->PWMC_CH[AT91C_PWMC_CHID0].PWMC_CMR =   AT91C_PWMC_CPRE_MCK_1024 | AT91C_PWMC_CPOL;