LPC17xx + PWM [aktualizacja częśtotliwości - rejestr MR0]

Cytat:

PWM mode is enabled (counter resets to 1). PWM mode causes the shadow
registers to operate in connection with the Match registers. A program write to a
Match register will not have an effect on the Match result until the corresponding
bit in PWMLER has been set, followed by the occurrence of a PWM Match 0
event. Note that the PWM Match register that determines the PWM rate (PWM
Match Register 0 - MR0) must be set up prior to the PWM being enabled.
Otherwise a Match event will not occur to cause shadow register contents to
become effective.

Freddie Chopin napisał:

Opis nie do końca jest jasny...