Dzielenie w VHDL. Liczby binarne stałoprzecinkowe.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Entity DIVIDER is
	port(
		CLK					: in std_logic; -- 8MHz input clock
		RESET				: in std_logic; -- Active Low reset signal
		NUMERATOR			: in std_logic_vector(7 downto 0); 
		DENOMINATOR			: in std_logic_vector(7 downto 0); 
		RESULT				: out std_logic_vector(7 downto 0);
                               READY				: out std_logic
	);
end DIVIDER;

architecture RTL of DIVIDER is

	signal DIV_REG : std_logic_vector(15 downto 0);
	signal CYCLE_COUNTER : std_logic_vector(3 downto 0);
begin
		
	DIV_PROCESS: process(NUMERATOR,DENOMINATOR,DIV_REG,RESET,CLK)
		begin
			if RESET='0' then
				DIV_REG<=(others=>'0');
			elsif CLK'event and CLK='1' then
				if CYCLE_COUNTER="1000" then
					DIV_REG(7 downto 0)<=NUMERATOR;
					DIV_REG(15 downto 8)<=(others=>'0');
					RESULT<=DIV_REG(7 downto 0);
                READY<='1';
				else
                                                                                READY<='0';
					if DIV_REG(14 downto 7)>=DENOMINATOR then
						DIV_REG(15 downto 8)<=DIV_REG(14 downto 7)-DENOMINATOR;
						DIV_REG(7 downto 1)<=DIV_REG(6 downto 0);
						DIV_REG(0)<='1';
					else
						DIV_REG(15 downto 1)<=DIV_REG(14 downto 0);
						DIV_REG(0)<='0';
					end if;
				end if;
			end if;
		end process;		
	
	CYCLE_COUNTER_PROCESS: process(CLK,RESET,CYCLE_COUNTER)
		begin
			if RESET<='0' then
				CYCLE_COUNTER<=(others=>'0');
			elsif CLK'event and CLK='1' then
				if CYCLE_COUNTER="1000" then
					CYCLE_COUNTER<=(others=>'0');
				else
					CYCLE_COUNTER<=CYCLE_COUNTER+1;
				end if;
			end if;
		end process;
		
end RTL;